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19-1388; Rev 0; 11/98
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX
General Description
The MAX157/MAX159 low-power, 10-bit analog-to-digital converters (ADCs) are available in 8-pin MAX and DIP packages. Both devices operate with a single +2.7V to +5.25V supply and feature a 7.4s successive-approximation ADC, automatic power-down, fast wake-up (2.5s), an on-chip clock, and a high-speed, 3-wire serial interface. Power consumption is only 3.2mW (VDD = +3.6V) at the maximum sampling rate of 108ksps. At slower throughput rates, the 0.2A automatic shutdown further reduces power consumption. The MAX157 provides 2-channel, single-ended operation and accepts input signals from 0 to VREF. The MAX159 accepts pseudo-differential inputs ranging from 0 to V REF . An external clock accesses data through the 3-wire serial interface, which is SPITM, QSPITM, and MICROWIRETM compatible. Excellent dynamic performance and low power, combined with ease of use and a small package size, make these converters ideal for battery-powered and data acquisition applications, or for other circuits with demanding power-consumption and space requirements. For pin-compatible 12-bit upgrades, see the MAX144/MAX145 data sheet.
Features
o Single-Supply Operation (+2.7V to +5.25V) o Two Single-Ended Channels (MAX157) Single Pseudo-Differential Channel (MAX159) o Low Power 0.9mA (at 108ksps, +3V) 100A (at 10ksps, +3V) 10A (at 1ksps, +3V) <0.2A (power-down mode) o Internal Track/Hold o 108ksps Sampling Rate o SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface o Space-Saving 8-Pin MAX Package o Pin-Compatible 12-Bit Upgrades Available
MAX157/MAX159
Ordering Information
PART TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 8 MAX 8 MAX 8 Plastic DIP 8 Plastic DIP 8 MAX 8 MAX 8 Plastic DIP 8 Plastic DIP 8 CERDIP* 8 CERDIP* 8 MAX 8 MAX 8 Plastic DIP 8 Plastic DIP 8 MAX 8 MAX 8 Plastic DIP 8 Plastic DIP 8 CERDIP* 8 CERDIP* INL (LSB) 0.5 1 0.5 1 0.5 1 0.5 1 0.5 1 0.5 1 0.5 1 0.5 1 0.5 1 0.5 1
Applications
Battery-Powered Systems Portable Data Logging Isolated Data Acquisition Process-Control Monitoring Instrumentation Test Equipment Medical Instruments System Supervision
MAX157ACUA MAX157BCUA MAX157ACPA MAX157BCPA MAX157AEUA MAX157BEUA MAX157AEPA MAX157BEPA
Pin Configuration
TOP VIEW
VDD 1 CH0 (CH+) 2 CH1 (CH-) 3 8 7 SCLK DOUT CS/SHDN REF
MAX157AMJA -55C to +125C MAX157BMJA -55C to +125C MAX159ACUA 0C to +70C MAX159BCUA 0C to +70C MAX159ACPA 0C to +70C MAX159BCPA 0C to +70C MAX159AEUA -40C to +85C MAX159BEUA -40C to +85C MAX159AEPA MAX159BEPA MAX159AMJA MAX159BMJA -40C to +85C -40C to +85C -55C to +125C -55C to +125C
MAX157 MAX159
6 5
GND 4
MAX/DIP
( ) ARE FOR MAX159 ONLY.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
*Contact factory for availability. 1
________________________________________________________________ Maxim Integrated Products
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX MAX157/MAX159
ABSOLUTE MAXIMUM RATINGS
VDD to GND. .............................................................-0.3V to +6V CH0, CH1 (CH+, CH-) to GND...................-0.3V to (VDD + 0.3V) REF to GND ................................................-0.3V to (VDD + 0.3V) Digital Inputs to GND ...............................................-0.3V to +6V DOUT to GND.............................................-0.3V to (VDD + 0.3V) DOUT Sink Current ............................................................ 25mA Continuous Power Dissipation (TA = +70C) MAX (derate 4.1mW/C above +70C) ......................330mW Plastic DIP (derate 9.09mW/C above +70C) ............727mW CERDIP (derate 8.00mW/C above +70C) .................640mW Operating Temperature Ranges MAX157/MAX159_C_A .......................................0C to +70C MAX157/MAX159_E_A ....................................-40C to +85C MAX157/MAX159_MJA................................. -55C to +125C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V DD = +2.7V to +5.25V, V REF = 2.5V, 0.1F capacitor at REF, f SCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX159, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching External reference, VREF = 2.5V 0.8 0.02 0.02 RES INL DNL MAX15_A MAX15_B No missing codes over temperature 10 0.5 1 0.5 2 2 Bits LSB LSB LSB LSB ppm/C LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (fIN (sine wave) = 10kHz, VIN = 2.5Vp-p, 108ksps, external fSCLK = 2.17MHz, CH- = GND for MAX159) Signal-to-Noise Ratio plus Distortion Total Harmonic Distortion (including 5th-order harmonic) Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Small-Signal Bandwidth Full-Power Bandwidth SINAD THD SFDR fIN = 65kHz, VIN = 2.5Vp-p (Note 4) -3dB rolloff 66 -70 70 -75 2.25 1.0 dB dB dB dB MHz MHz
2
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+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX
ELECTRICAL CHARACTERISTICS (continued)
(V DD = +2.7V to +5.25V, V REF = 2.5V, 0.1F capacitor at REF, f SCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX159, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER CONVERSION RATE Conversion Time (Note 5) T/H Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency ANALOG INPUTS Analog Input Voltage Range (Note 6) Multiplexer Leakage Current Input Capacitance EXTERNAL REFERENCE Input Voltage Range (Note 7) Input Current Input Resistance Shutdown REF Input Current DIGITAL INPUTS (CS/SHDN, SCLK) AND DIGITAL OUTPUT (DOUT) VDD 3.6V Input High Voltage VIH VDD > 3.6V Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance Output Low Voltage Output High Voltage Three-State Output Leakage Current Three-State Output Capacitance COUT VIL VHYS IIN CIN VOL VOH VIN = 0 or VDD (Note 8) ISINK = 5mA ISINK = 16mA ISOURCE = 0.5mA CS/SHDN = VDD CS/SHDN = VDD (Note 8) VDD - 0.5 10 15 0.5 0.2 1 15 0.4 2.0 3.0 0.8 VREF VREF = 2.5V 18 0 VDD + 50mV 100 25 0.01 10 140 V A k A CIN VIN On/off-leakage current, VIN = 0 to VDD 0 0.01 16 VREF 1 V A A fSCLK External clock mode Internal clock mode, for data transfer only 0.1 0 tCONV tACQ 25 <50 2.17 5 External clock, fSCLK = 2.17MHz, 16 clock cycles per conversion Internal clock 7.4 5 7 2.5 s ns ps MHz MHz s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX157/MAX159
V V V A pF V V A pF
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3
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX MAX157/MAX159
ELECTRICAL CHARACTERISTICS (continued)
(V DD = +2.7V to +5.25V, V REF = 2.5V, 0.1F capacitor at REF, f SCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX159, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER POWER REQUIREMENTS Positive Supply Voltage Positive Supply Current Positive Supply Current Power-Supply Rejection (Note 9) VDD IDD IDD PSR Operating mode Shutdown, CS/SHDN = GND VDD = 2.7V to 5.25V, full-scale input +2.7 0.9 0.2 0.15 +5.25 2.0 5 V mA A mV SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Figure 7)
(V DD = +2.7V to +5.25V, V REF = 2.5V, 0.1F capacitor at REF, f SCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX159, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Wake-Up Time CS/SHDN Fall to Output Enable CS/SHDN Rise to Output Disable SCLK Fall to Output Data Valid SCLK Clock Frequency SYMBOL tWAKE tDV tTR tDO fSCLK CL = 100pF (Figure 1) CL = 100pF (Figure 1) CL = 100pF External clock Internal clock, SCLK for data transfer only External clock SCLK Pulse Width High tCH Internal clock, SCLK for data transfer only (Note 8) External clock SCLK Pulse Width Low SCLK to CS/SHDN Setup CS/SHDN Pulse Width tCL tSCLKS tCS Internal clock, SCLK for data transfer only (Note 8) 20 0.1 0 215 50 215 50 60 60 ns ns ns ns CONDITIONS MIN 2.5 120 120 120 2.17 5 TYP MAX UNITS s ns ns ns MHz
Note 1: Tested at VDD = +2.7V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been calibrated. Note 3: Offset nulled. Note 4: The on channel is grounded; the sine wave is applied to off channel (MAX157 only). Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs is from GND to VDD (MAX159 only). Note 7: ADC performance is limited by the converter's noise floor, typically 300Vp-p. Note 8: Guaranteed by design. Not subject to production testing. Note 9: Measured as VFS(2.7V) - VFS(5.25V).
4
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+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX
Typical Operating Characteristics
(VDD = +3.0V, VREF = 2.5V, 0.1F capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for MAX159; TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX157/159 toc01
MAX157/MAX159
SUPPLY CURRENT vs. TEMPERATURE
MAX157/159 toc02
SUPPLY CURRENT vs. SAMPLING RATE
VREF = VDD CODE = 1010101000 CL = 50pF
MAX157/159 toc03
1500 VREF = VDD RL = CL = 50pF CODE = 1010101000
1500 VREF = VDD RL = CL = 50pF CODE = 1010101000
10,000
1300 SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
1100
SUPPLY CURRENT (A)
1250
1000
100
1000
900
10
750 700
1 500 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C)
500
0.1 0.1 1 10 100 1k 10k 100k SAMPLING RATE (sps)
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
VREF = VDD SHUTDOWN CURRENT (nA) 800
MAX157/159 toc04
SHUTDOWN CURRENT vs. TEMPERATURE
VREF = VDD SHUTDOWN CURRENT (nA) 800
MAX157/159 toc05
1000
1000
600
600
400
400
200
200
0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5
0 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX157/159 toc06
OFFSET ERROR vs. TEMPERATURE
MAX157/159 toc07
0.20
0.20
OFFSET ERROR (LSB)
OFFSET ERROR (LSB)
0.15
0.15
0.10
0.10
0.05
0.05
0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5
0 -60 -35 -10 15 40 65 90 115 140 TEMPERATURE (C)
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5
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX MAX157/MAX159
Typical Operating Characteristics (continued)
(VDD = +3.0V, VREF = 2.5V, 0.1F capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for MAX159; TA = +25C, unless otherwise noted.)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX157/159 toc08
GAIN ERROR vs. TEMPERATURE
MAX157/159 toc09
INTEGRAL NONLINEARITY vs. OUTPUT CODE
MAX157/8 toc10
0.2
0.2
0.03 0.02 0.01 INL (LSB)
0.1 GAIN ERROR (LSB)
0.1 GAIN ERROR (LSB)
0
0
0 -0.01
-0.1
-0.1 -0.02
-0.2 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5
-0.2 -60 -35 -10 15 40 65 90 115 140 TEMPERATURE (C)
-0.03 0 250 500 OUTPUT CODE 750 1000
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX157/159 toc11
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX157/159 toc12
0.20
0.20
0.15 INL (LSB)
0.15 INL (LSB)
0.10
0.10
0.05
0.05
0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5
0 -60 -35 -10 15 40 65 90 115 140 TEMPERATURE (C)
6
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+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME VDD CH0 (CH+) CH1 (CH-) GND REF CS/SHDN DOUT SCLK Positive Supply Voltage, +2.7V to +5.25V Analog Input, MAX157: Single-Ended (CH0); MAX159: Differential (CH+). Analog Input, MAX157: Single-Ended (CH1); MAX159: Differential (CH-). Analog and Digital Ground External Reference Voltage Input. Sets analog voltage range. Bypass with a 100nF capacitor close to the part. Active-Low Chip-Select Input, Active-High Shutdown Input. Pulling CS/SHDN high puts chip into shutdown with a maximum current of 5A. Serial Data Output. Data changes state at SCLK's falling edge. High impedance when CS/SHDN is high. Serial Clock Input. DOUT changes on the falling edge of SCLK. FUNCTION
MAX157/MAX159
VDD DOUT DOUT 6k GND a) HIGH-Z TO V0H, V0L TO V0H, AND VOH TO HIGH-Z CL CL GND b) HIGH-Z TO V0L, V0H TO V0L, AND VOL TO HIGH-Z 6k
Figure 1. Load Circuits for Enable and Disable Time
Detailed Description
The MAX157/MAX159 analog-to-digital converters (ADCs) use a successive-approximation conversion (SAR) technique and on-chip track/hold (T/H) structure to convert an analog signal to a serial, 10-bit digital output data stream. This flexible serial interface provides easy interface to microprocessors (Ps). Figure 2 shows a simplified functional diagram of the internal architecture for both the MAX157 (2 channels, single-ended) and the MAX159 (1 channel, pseudo-differential).
the same channel by toggling CS/SHDN twice between conversions. If only one channel is required, CH0 and CH1 may be connected together; however the output data will still contain the channel identification bit (before the MSB). For the MAX159, the input channels form a single differential channel pair (CH+, CH-). This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side IN- must remain stable within 0.5LSB (0.1LSB for optimum results) with respect to GND during a conversion. To accomplish this, connect a 0.1F capacitor from IN- to GND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans from when CS/SHDN falls to the falling edge of the second clock cycle (external clock mode) or from when CS/SHDN falls to the first falling edge of SCLK (internal clock mode). At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). This unbalances node ZERO at the comparator's positive input.
7
Single-Ended (MAX157) and PseudoDifferential (MAX159) Analog Inputs
The sampling architecture of the ADC's analog comparator is illustrated in the equivalent input circuit in Figure 3. In single-ended mode (MAX157), both channels CH0 and CH1 are referred to GND and can be connected to two different signal sources. Following the power-on reset, the ADC is set to convert CH0. After CH0 has been converted, CH1 will be converted, and the conversions will continue to alternate between channels. Channel switching is performed by toggling the CS/SHDN pin. Conversions can be performed on
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+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX MAX157/MAX159
The capacitive digital-to-analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 10-bit resolution. This action is equivalent to transferring a 16pF * [(VIN+) - (VIN-)] charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. Higher source impedances can be used if a 0.01F capacitor is connected to the individual analog inputs. Together with the input impedance, this capacitor forms an RC filter, limiting the ADC's signal bandwidth.
Input Bandwidth
The MAX157/MAX159 T/H stage offers both a 2.25MHz small-signal and a 1MHz full-power bandwidth, which makes it possible to use the parts for digitizing highspeed transients and measuring periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Most aliasing problems can be fixed easily with an external resistor and a capacitor. However, if DC precision is required, it is usually best to choose a continuous or switched-capacitor filter, such as the MAX7410/ MAX7414 (Figure 4). Their Butterworth characteristic generally provides the best compromise (with regard to rolloff and attenuation) in filter configurations, is easy to design, and provides a maximally flat passband response.
Track/Hold
The ADC's T/H stage enters its tracking mode on the falling edge of CS/SHDN. For the MAX157 (singleended inputs), IN- is connected to GND and the converter samples the positive ("+") input. For the MAX159 (pseudo-differential inputs), IN- connects to the negative input ("-"), and the difference of [(VIN+) - (VIN-)] is sampled. At the end of the conversion, the positive input connects back to IN+ and CHOLD charges to the input signal. The time required for the T/H stage to acquire an input signal is a function of how fast its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal, and is also the minimum time required for the signal to be acquired. Calculate this with the following equation: tACQ = 7(RS + RIN)CIN where RS is the source impedance of the input signal, RIN (9k) is the input resistance, and CIN (16pF) is the input capacitance of the ADC. Source impedances below 4k have no significant impact on the AC performance of the MAX157/MAX159.
Analog Input Protection
Internal protection diodes, which clamp the analog input to VDD and GND, allow each input channel to swing within GND - 300mV to VDD + 300mV without damage. However, for accurate conversions both inputs must not exceed VDD + 50mV or be less than GND - 50mV. If an off-channel analog input voltage exceeds the supplies, limit the input current to 4mA.
CAPACITIVE DAC CS/SHDN SCLK INTERNAL CLOCK CONTROL LOGIC CH0 (CH+) CH1 (CH-) REF ( ) ARE FOR MAX159 ANALOG INPUT MUX (2 CHANNEL) T/H OUTPUT REGISTER DOUT CH1 (CH-) CH0 (CH+) CSWITCH SCLK 10+2 BIT IN SAR OUT ADC TRACK HOLD T/H GND SINGLE-ENDED MODE: CHO, CH1 = IN+; GND = INDIFFERENTIAL MODE: CH+ = IN+; CH- = INCONTROL LOGIC ( ) ARE FOR MAX159 REF INPUT MUX - COMPARATOR + CHOLD 16pF RIN 9k ZERO TO SAR
MAX157 MAX159
Figure 2. MAX157/MAX159 Simplified Functional Diagram
8
Figure 3. Analog Input Channel Structure
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+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX
Selecting Clock Mode
To start the conversion process on the MAX157/ MAX159, pull CS/SHDN low. At CS/SHDN's falling edge, the part wakes up, the internal T/H enters track mode, and a conversion begins. In addition, the state of SCLK at CS/SHDN's falling edge selects internal (SCLK = high) or external (SCLK = low) clock mode. ing SCLK high during a high/low transition of CS/SHDN. The first SCLK falling edge samples the data and initiates a conversion using the integrated on-chip oscillator. After the conversion, the oscillator shuts off and DOUT goes high, signaling the end of conversion (EOC). Data can then be read out with SCLK.
MAX157/MAX159
Internal Clock (fSCLK < 100kHz or fSCLK > 2.17MHz) In internal clock mode, the MAX157/MAX159 run from an internal, laser-trimmed oscillator to within 20% of the 2MHz specified clock rate. This releases the system microprocessor from running the SAR conversion clock and allows the conversion results to be read back at the processor's convenience, at any clock rate from 0 to 5MHz. Operating the MAX157/MAX159 in internal clock mode is necessary for serial interfaces operating with clock frequencies lower than 100kHz or greater than 2.17MHz. Select internal clock mode (Figure 5) by hold-
External Clock (fSCLK = 100kHz to 2.17MHz) External clock mode (Figure 6) is selected by transitioning CS/SHDN from high to low while SCLK is low. The external clock signal not only shifts data out, but also drives the analog-to-digital conversion. The input is sampled and conversion begins on the falling edge of the second clock pulse. Conversion must be completed within 140s to prevent degradation in the conversion results caused by droop on the T/H capacitors. External clock mode provides the best throughput for clock frequencies between 100kHz and 2.17MHz.
VDD
4 VDD
SHDN
7 470
0.1F
2
CH0
1 VDD
REF
5
EXTERNAL REFERENCE
2 fCORNER = 15kHz
IN
MAX7410 MAX7414
OUT 5 8 CLK
MAX157
3 0.01F 8 6 CH1 DOUT 7
COM 1 0.01F
OS 6
GND 3 1.5MHz CLOCK
SCLK
GND 4
CS/SHDN
P/C
Figure 4. Analog Input with Anti-Aliasing Filter Structure
ACTIVE
POWER DOWN tCS
ACTIVE tWAKE (tACQ) tCONV
CS/SHDN SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HIGH-Z
DOUT
HIGH-Z SAMPLING INSTANT
EOC
1
1 CHID MSB D8
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
Figure 5. Internal Clock Mode Timing
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+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX MAX157/MAX159
Output Data Format
Table 1 illustrates the 16-bit, serial data-stream output format for both the MAX157 and MAX159. The first three bits are always logic high (including the EOC bit for internal clock mode), followed by the channel identification (CHID = 0 for CH0, CHID = 1 for CH1, CHID = 1 for MAX159), the 10 bits of data in MSB first format, and two sub-LSB bits (S1 and S0). After the last bit has been read out, additional SCLK pulses will clock out trailing zeros. DOUT transitions on the falling edge of SCLK. The output remains high impedance when CS/SHDN is high.
Automatic Power-Down Mode
Whenever the MAX157/MAX159 are not selected (CS/SHDN = VDD), the parts enter their shutdown mode. In shutdown all internal circuitry is turned off, which reduces the supply current to typically less than 0.2A. With an external reference stable to within 1LSB, the wake-up time is 2.5s. If the external reference is not stable within 1LSB, the wake-up time must be increased to allow the reference to stabilize.
Applications Information
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, SNR is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR(MAX) = (6.02 * N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
External Reference
An external reference is required for both the MAX157 and MAX159. At REF, the DC input resistance is a minimum of 18k. During a conversion, a reference must be able to deliver 250A of DC load current and have an output impedance of 10 or less. Use a 0.1F bypass capacitor for best performance. The reference input structure allows a voltage range of 0 to (VDD + 50mV) although noise levels will decrease effective resolution at lower reference voltages.
ACTIVE
POWER DOWN tCS
ACTIVE SAMPLING INSTANT tWAKE (tACQ)
CS/SHDN SCLK HIGH-Z DOUT 1 2 3 4 5 6 7 D7 8 D6 9 D5 10 D4 11 D3 12 D2 13 D1 14 D0 15 S1 16 S0 HIGH-Z
CHID MSB D8
Figure 6. External Clock Mode Timing
CS/SHDN
***
tSCLKS
tCL
tCH
tCS
SCLK
***
tDV DOUT HIGH-Z ***
tDO
tTR HIGH-Z
Figure 7. Detailed Serial-Interface Timing Sequence
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+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX
Table 1. Serial Output Data Stream for Internal and External Clock Mode
SCLK CYCLE DOUT (Internal Clock) DOUT (External Clock) 1 EOC 1 2 1 1 3 1 1 4 5 6 D8 D8 7 D7 D7 8 D6 D6 9 D5 D5 10 D4 D4 11 D3 D3 12 D2 D2 13 D1 D1 14 D0 D0 15 S1 S1 16 S0 S0 CHID D9 CHID D9
MAX157/MAX159
etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise (which includes all spectral components minus the fundamental), the first five harmonics, and the DC offset.
serial clock for the MAX157/MAX159. Select a clock frequency from 100kHz to 2.17MHz (external clock mode). 1) Use a general-purpose I/O line on the CPU to pull CS/SHDN low while SCLK is low. 2) Wait for the minimum wake-up time (tWAKE) specified before activating SCLK. 3) Activate SCLK for a minimum of 16 clock cycles. The first falling clock edge will generate a serial datastream of three leading ones, followed by the channel identification, the MSB of the digitized input signal, and two sub-bits. DOUT transitions on SCLK's falling edge and is available in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Data should be clocked into the P on SCLK's rising edge. 4) Pull CS/SHDN high at or after the 16th falling clock edge. If CS/SHDN remains low, trailing zeros will be clocked out after the sub-bits. 5) With CS/SHDN high, wait at least 60ns (tCS), before starting a new conversion by pulling CS/SHDN low. A conversion can be aborted by pulling CS/SHDN high before the conversion ends; wait at least 60ns before starting a new conversion. Data can be output either in two 8-bit sequences or continuously. The bytes will contain the result of the conversion padded with three leading ones, the channel identification before the MSB, and two trailing subbits. If the serial clock hasn't been idled after the last sub-bit (S0) and CS/SHDN is kept low, DOUT sends trailing zeros.
Signal-to-Noise Plus Distortion (SINAD)
Signal-to-noise plus distortion is the ratio of the fundamental input frequency's RMS amplitude to RMS equivalent of all other ADC output signals: SINAD(dB) = 20
log (Noise SignalRMS + Distortion)
RMS

Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:
THD = 20
log
(V
22 + V32 + V4 2 + V52
V12
)

where V1 is the fundamental amplitude and V2 through V5 are the amplitudes of the 2nd through 5th-order harmonics.
SPI and MICROWIRE Interface
When using SPI (Figure 8a) or MICROWIRE (Figure 8b) interfaces, set CPOL = 0 and CPHA = 0. Conversion begins with a falling edge on CS/SHDN (Figure 8c). Two consecutive 8-bit readings are necessary to obtain the entire 10-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the P on SCLK's rising edge. The first 8-bit data stream contains three leading ones, followed by channel identification and the first four data bits starting with the MSB. The second 8-bit data stream contains the remaining bits, D5 through D0, and the sub-bits S1 and S0.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.
Connection to Standard Interfaces
The MAX157/MAX159 interface is fully compatible with SPI/QSPI and MICROWIRE standard serial interfaces. If a serial interface is available, establish the CPU's serial interface as master so that the CPU generates the
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11
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX MAX157/MAX159
I/O SCK MISO CS/SHDN SCLK DOUT VDD I/O SK SI CS/SHDN SCLK DOUT
SPI
MICROWIRE
MAX157 MAX159
SS
MAX157 MAX159
Figure 8a. SPI Connections
Figure 8b. MICROWIRE Connections
1ST BYTE READ SCLK CS/SHDN DOUT* SAMPLING INSTANT *WHEN CS/SHDN IS HIGH, DOUT = HIGH -Z 1 2 3 4 5 6 7 8 9 10 11
2ND BYTE READ 12 13 14 15 16
CHID
D9 MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0 LSB
S1
S0
HIGH-Z
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0 and CPHA = 0, the MAX157/MAX159 supports a maximum fSCLK of 2.17MHz. The QSPI circuit in Figure 9a can be programmed to perform a conversion on each of the two channels for the MAX157. Figure 9b shows the QSPI interface timing.
CS SCK MISO CS/SHDN SCLK DOUT VDD
QSPI
PIC16 with SSP Module and PIC17 Interface
The MAX157/MAX159 are compatible with a PIC16/ PIC17 microcontroller (C), using the synchronous serial port (SSP) module. To establish SPI communication, connect the controller as shown in Figure 10a and configure the PIC16/PIC17 as system master by initializing its synchronous serial port control register (SSPCON) and synchronous serial port status register (SSPSTAT) to the bit patterns shown in Tables 2 and 3. In SPI mode, the PIC16/PIC17 Cs allow eight bits of data to be synchronously transmitted and received simultaneously. Two consecutive 8-bit readings (Figure 10b) are necessary to obtain the entire 10-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the C on SCLK's rising edge. The first 8-bit data stream contains
12
SS
MAX157 MAX159
Figure 9a. QSPI Connections
three leading ones, the channel identification, and the first four data bits starting with the MSB. The second 8bit data stream contains the remaining bits, D5 through D0, and the two sub-bits S1 and S0.
Layout, Grounding, and Bypassing
For best performance use printed circuit boards (PCBs), wire-wrap configurations are not recommended, since the layout should ensure proper separation of analog and digital traces. Run analog and digital lines anti-parallel to each other, and don't layout digital signal paths underneath the ADC package. Use separate analog and digital PCB ground sections with only one
______________________________________________________________________________________
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX MAX157/MAX159
SCLK CS/SHDN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
HIGH-Z DOUT CHID D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB S1 S0 SAMPLING INSTANT *WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
VDD VDD
SCLK DOUT CS/SHDN
SCK SDI I/O
MAX157 MAX159
GND
PIC16/PIC17
GND
Figure 10a. SPI Interface Connection for a PIC16/PIC17 Controller
star-point (Figure 11) connecting the two ground systems (analog and digital). For lowest-noise operation, ensure the ground return to the star ground's power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply (VDD) could influence the proper operation of the ADC's fast comparator. Bypass VDD to the star ground with a network of two parallel capacitors, 0.1F and 1F, located as close as possible to the power supply pin of the MAX157/MAX159. Minimize capacitor lead length for best supply-noise rejection and add an attenuation resistor (10) if the power supply is extremely noisy.
1ST BYTE READ SCLK CS/SHDN 1 2 3 4 5 6 7 8 9 10 11
2ND BYTE READ 12 13 14 15 16
HIGH-Z DOUT* CHID D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB S1 S0 SAMPLING INSTANT *WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z
Figure 10b. SPI Interface Timing Sequence with PIC16/17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3-SSPM0 = 0001)
POWER SUPPLIES +3V R* = 10 1F +3V GND
0.1F VDD GND +3V DGND
MAX157 MAX159
* OPTIONAL FILTER RESISTOR
DIGITAL CIRCUITRY
Figure 11. Power-Supply Bypassing and Grounding
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+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX MAX157/MAX159
Table 2. Detailed SSPCON Register Content
CONTROL BIT WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MAX157/MAX159 SETTINGS X X 1 0 0 0 0 1 Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects fCLK = fOSC / 16. SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON) Write Collision Detection Bit Receive Overflow Detect Bit Synchronous Serial Port Enable Bit 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins. Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
X = Don't care
Table 3. Detailed SSPSTAT Register Content
CONTROL BIT SMP CKE D/A P S R/W UA BF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MAX157/MAX159 SETTINGS 0 1 X X X X X X SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT) SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time. SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock. Data Address Bit Stop Bit Start Bit Read/Write Bit Information Update Address Buffer Full Status Bit
X = Don't care
14
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+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX
Chip Information
TRANSISTOR COUNT: 2,058 SUBSTRATE CONNECTED TO GND
MAX157/MAX159
Package Information
8LUMAXD.EPS
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15
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX MAX157/MAX159
Package Information (continued)
PDIPN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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